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1 ? fn9202.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6251, isl6251a low cost multi-chemistry battery charger controller the isl6251, isl6251a is a highly integrated battery charger controller for li-ion/li-ion polymer batteries and nimh batteries. high efficiency is achieved by a synchronous buck topology and the use of a mosfet, instead of a diode, for selecting power from the adapter or battery. the low side mosfet emulates a diode at light loads to improve the light load efficiency and prevent system bus boosting. the constant output voltage c an be selected for 2, 3 and 4 series li-ion cells with 0.5% accuracy over temperature. it can be also programmed between 4.2v+5%/cell and 4.2v-5%/cell to optimize battery capacity. when supplying the load and battery charger simultaneously, the input current limit for the ac adapte r is programmable to within 3% accuracy to avoid overloading the ac adapter, and to allow the system to make efficient use of available adapter power for charging. it also has a wide range of programmable charging current. the isl6251, isl6251a provides outputs that are used to monitor the current drawn from the ac adapter, and monitor for the presence of an ac adapter. the isl6251, isl6251a automatically transitions from regulating current mode to regulating voltage mode. features ? 0.5% charge voltage accuracy (-10c to 100c) ? 3% accurate input current limit ? 5% accurate battery charge current limit ? 25% accurate battery trickle charge current limit (isl6251a) ? programmable charge current limit, adapter current limit and charge voltage ? fixed 300khz pwm synchronous buck controller with diode emulation at light load ? output for current dr awn from ac adapter ? ac adapter present indicator ? fast input current limit response ? input voltage range 7v to 25v ? support 2, 3 and 4 cells battery pack ? up to 17.64v battery-voltage set point ? thermal shutdown ? support pulse charging ? less than 10a battery leakage current ? charge any battery chemistr y: li-ion, nicd, nimh, etc. ? pb-free plus anneal available (rohs compliant) applications ? notebook, desknote and sub-notebook computers ? personal digital assistant ordering information part number temp range (c) package pkg. dwg. # ISL6251HRZ (notes 1, 2) -10 to 100 28 ld 5x5 qfn (pb-free) l28.5 5 isl6251haz (notes 1, 2) -10 to 100 24 ld qsop (pb-free) m24.15 isl6251ahrz (notes 1, 2) -10 to 100 28 ld 5x5 qfn (pb-free) l28.5 5 isl6251ahaz (notes 1, 2) -10 to 100 24 ld qsop (pb-free) m24.15 notes: 1. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. add ?-t? for tape and reel. data sheet june 17, 2005
2 fn9202.1 june 17, 2005 pinouts isl6251, isl6251a (28 ld qfn) top view isl6251, isl6251a (24 ld qsop) top view 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 en cells icomp vcomp icm vref chlim aclim pgnd lgate vddp boot csop phase ugate acset dcin acprn cson vadj gnd csin csip na na na vdd na dcin 124 vdd 223 acprn acset 322 cson 421 csop en 520 csin cells 619 csip icomp 718 vcomp 817 icm 916 phase vref 10 15 ugate chlim 11 14 boot aclim 12 13 vddp vadj lgate gnd pgnd isl6251, isl6251a
3 fn9202.1 june 17, 2005 absolute maximum rati ngs thermal information dcin, csip, cson to gnd. . . . . . . . . . . . . . . . . . . . . -0.3v to +28v csip-csin, csop-cson . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v phase to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7v to 30v boot to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +35v boot-phase, vdd-gnd, vddp-pgnd, acprn to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v acset to gnd (note 3) . . . . . . . . . . . . . . . . . . -0.3v to vdd+0.3v icm, icomp, vcomp to gnd. . . . . . . . . . . . . . -0.3v to vdd+0.3v aclim, chlim, vref, cells to gnd . . . . . . . -0.3v to vdd+0.3v en, vadj, pgnd to gnd . . . . . . . . . . . . . . . . . .-0.3v to vdd+0.3v ugate. . . . . . . . . . . . . . . . . . . . . . . . . phase-0.3v to boot+0.3v lgate . . . . . . . . . . . . . . . . . . . . . . . . . . pgnd-0.3v to vddp+0.3v thermal resistance ja (c/w) jc (c/w) qfn package (notes 4, 6). . . . . . . . . . 39 9.5 qsop package (note 5) . . . . . . . . . . . 88 n/a esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 2 junction temperature range. . . . . . . . . . . . . . . . . .-10c to +150c operating temperature range . . . . . . . . . . . . . . . .-10c to +100c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 3. when the voltage across acset is below 0v, the curr ent through acset should be limited to less than 1ma. 4. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fea tures. see tech brief tb379. 5. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications dcin=csip=csin=18v, csop=cson=12v, acset=1.5 v, aclim=vref, vadj=floating, en=vdd=5v, boot-phase=5.0v, gnd=pgnd=0v, c vdd =1f, i vdd =0ma, t a =-10c to +100c, t j 125c, unless otherwise noted. parameter test conditions min typ max units supply and bias regulator dcin input voltage range 7 25 v dcin quiescent current en=vdd or gnd, 7v dcin 25v 1.4 3 ma battery leakage current (note 7) dcin=0, no load 3 10 a vdd output voltage/regulation 7v dcin 25v, 0 i vdd 30ma 4.925 5.075 5.225 v vdd undervoltage lockout trip point vdd rising 4.0 4.4 4.6 v hysteresis 200 250 400 mv reference output voltage vref 0 i vref 300a 2.365 2.39 2.415 v battery charge voltage accuracy cson=16.8v, cells=vdd, vadj=float -0.5 0.5 % cson=12.6v, cells=gnd, vadj=float -0.5 0.5 % cson=8.4v, cells=float, vadj=float -0.5 0.5 % cson=17.64v, cells=vdd, vadj=vref -0.5 0.5 % cson=13.23v, cells=gnd, vadj=vref -0.5 0.5 % cson=8.82v, cells=float, vadj=vref -0.5 0.5 % cson=15.96v, cells=vdd, vadj=gnd -0.5 0.5 % cson=11.97v, cells=gnd, vadj=gnd -0.5 0.5 % cson=7.98v, cells=float, vadj=gnd -0.5 0.5 % trip points acset threshold 1.24 1.26 1.28 v acset input bias current hysteresis 2.2 3.4 4.4 a acset input bias current acset 1.26v 2.2 3.4 4.4 a acset input bias current acset < 1.26v -1 0 1 a isl6251, isl6251a
4 fn9202.1 june 17, 2005 oscillator frequency 245 300 355 khz pwm ramp voltage (peak-peak) csip=18v 1.6 v csip=11v 1 v synchronous buck regulator maximum duty cycle 97 99 99.6 % ugate pull-up resistance boot-phase=5v, 500ma source current 1.8 3.0 ? ugate source current boot-phase=5v, boot-ugate=2.5v 1.0 a ugate pull-down resistance boot-phase=5v, 500ma sink current 1.0 1.8 ? ugate sink current boot-phase=5v, ugate-phase=2.5v 1.8 a lgate pull-up resistance vddp-pgnd=5v, 500ma source current 1.8 3.0 ? lgate source current vddp-pgnd=5v, vddp-lgate=2.5v 1.0 a lgate pull-down resistance vddp-pgnd=5v, 500ma sink current 1.0 1.8 ? lgate sink current vddp-pgnd=5v, lgate=2.5v 1.8 a charging current sensing amplifier input common-mode range 0 18 v input offset voltage guarantee by design -2.5 0 2.5 mv input bias current at csop 0 < csop < 18v 0.25 2 a input bias current at cson 0 < cson < 18v 75 100 a chlim input voltage range 0 3.6 v csop to cson full-scale current sense voltage isl6251: chlim=3.3v 157 165 173 mv isl6251a, chlim=3.3v 160 165 170 mv isl6251: chlim=2.0v 95 100 105 mv isl6251a: chlim=2.0v 97 100 103 mv isl6251: chlim=0.2v 5.0 10 15.0 mv isl6251a: chlim=0.2v 7.5 10 12.5 mv chlim input bias current chlim=gnd or 3.3v, dcin=0v -1 1 a chlim power-down mode threshold voltage chlim rising 80 88 95 mv chlim power-down mode hysteresis voltage 15 25 40 mv adapter current sensing amplifier input common-mode range 7 25 v input offset voltage guarantee by design -2 2 mv input bias current at csip & csin combined csip=csin=25v 100 130 a input bias current at csin 0 < csin < dcin, guaranteed by design 0.10 1 a electrical specifications dcin=csip=csin=18v, csop=cson=12v, acset=1.5 v, aclim=vref, vadj=floating, en=vdd=5v, boot-phase=5.0v, gnd=pgnd=0v, c vdd =1f, i vdd =0ma, t a =-10c to +100c, t j 125c, unless otherwise noted. (continued) parameter test conditions min typ max units isl6251, isl6251a
5 fn9202.1 june 17, 2005 adapter current limit threshold csip to csin full-scale current sense voltage aclim=vref 97 100 103 mv aclim=float 72 75 78 mv aclim=gnd 47 50 53 mv aclim input bias current aclim=vref 10 16 20 a aclim=gnd -20 -16 -10 a voltage regulation error amplifier error amplifier transconductance from cson to vcomp cells=vdd 30 a/v current regulation error amplifier charging current error amplifier transconductance 50 a/v adapter current error amplifier transconductance 50 a/v battery cell selector cells input voltage for 4 cell select 4.3 v cells input voltage for 3 cell select 2v cells input voltage for 2 cell select 2.1 4.2 v logic interface en input voltage range 0 vdd v en threshold voltage rising 1.030 1.06 1.100 v falling 0.985 1.000 1.025 v hysteresis 30 60 90 mv en input bias current en=2.5v 1.8 2.0 2.2 a acprn sink current acprn=0.4v 3 8 11 ma acprn leakage current acprn=5v -0.5 0.5 a icm output accuracy (vicm=19.9 x (vcsip-vcsin)) csip-csin=100mv -3 0 +3 % csip-csin=75mv -4 0 +4 % csip-csin=50mv -5 0 +5 % thermal shutdown temperature 150 c thermal shutdown temperature hysteresis 25 c note: 7. this is the sum of currents in these pins (csip, csin, boot, ugate, phase, csop, cson) all tied to 16.8v. no current in pins en, acset, vadj, cells, aclim, chlim. electrical specifications dcin=csip=csin=18v, csop=cson=12v, acset=1.5 v, aclim=vref, vadj=floating, en=vdd=5v, boot-phase=5.0v, gnd=pgnd=0v, c vdd =1f, i vdd =0ma, t a =-10c to +100c, t j 125c, unless otherwise noted. (continued) parameter test conditions min typ max units isl6251, isl6251a
6 fn9202.1 june 17, 2005 typical operating performance dcin=20v, 4s2p li-battery, t a =25c, unless otherwise noted. figure 1. vdd load regulation figure 2. vref load regulation figure 3. icm accuracy vs ac adapter current fi gure 4. system efficiency vs charge current figure 5. load transient response fig ure 6. charger enable & shutdown -0.6 -0.3 0 0.3 0.6 0 8 16 24 32 40 vdd load regulation accuracy (%) vdd=5.075v en=0 load current (ma) -0.6 -0.3 0 0.3 0.6 0 8 16 24 32 40 vdd load regulation accuracy (%) vdd=5.075v en=0 load current (ma) 0 0.02 0.04 0.06 0.08 0.1 0 100 200 300 400 vref load regulation accuracy (%) vref=2.390v load current (a) 0 0.02 0.04 0.06 0.08 0.1 0 100 200 300 400 vref load regulation accuracy (%) vref=2.390v load current (a) csip-csin (mv) 0 1 2 3 4 5 6 7 8 9 10 10 20 30 40 50 60 70 80 90 100 | icm accuracy | (%) 0.76 0.8 0.84 0.88 0.92 0.96 1 00.511.522.533.54 efficiency (%) charge current (a) vcson=16.8v 4 cells vcson=12.6v (3 cells) vcson=8.4v 2 cells 0.76 0.8 0.84 0.88 0.92 0.96 1 00.511.522.533.54 efficiency (%) charge current (a) vcson=16.8v 4 cells vcson=12.6v (3 cells) vcson=8.4v 2 cells load current 5a/div a dapter current 5a/div charge current 2a/div battery voltage 2v/div load step: 0-4a charge current: 3a a c adapter current limit: 5.15 a cson 5v/div en 5v/div inductor current 2a/div charge current 2a/div cson 5v/div en 5v/div inductor current 2a/div charge current 2a/div isl6251, isl6251a
7 fn9202.1 june 17, 2005 figure 7. battery insertion and removal figure 8. switching waveforms at diode emulation figure 9. switching waveforms in cc mode figure 10. trickle to full-scale charging typical operating performance dcin=20v, 4s2p li-battery, t a =25c, unless otherwise noted. (continued) inductor current 2a/div cson 10v/div vcomp icomp battery insertion battery removal vcomp 2v/div icomp 2v/div inductor current 2a/div cson 10v/div vcomp icomp battery insertion battery removal vcomp 2v/div icomp 2v/div phase 10v/div inductor current 1a/div ugate 5v/div chlim=0.2v cson=8v phase 10v/div inductor current 1a/div ugate 5v/div phase 10v/div inductor current 1a/div ugate 5v/div chlim=0.2v cson=8v phase 10v/div lgate 2v/div ugate 2v/div phase 10v/div lgate 2v/div ugate 2v/div chlim 1v/div charge current 1a/div isl6251, isl6251a
8 fn9202.1 june 17, 2005 functional pin descriptions boot connect boot to a 0.1f ceramic capacitor to phase pin and connect to the cathode of the bootstrap schottky diode. ugate ugate is the high side mosfet gate drive output. lgate lgate is the low side mosfet gate drive output; swing between 0v and vddp. phase the phase connection pin connects to the high side mosfet source, output inductor, and low side mosfet drain. csop/cson csop/cson is the battery charging current sensing positive/negative input. the di fferential voltage across csop and cson is used to sense the battery charging current, and is compared with the charging current limit threshold to regulate the charging current. the cson pin is also used as the battery feedback voltage to perform voltage regulation. csip/csin csip/csin is the ac adapter current sensing positive/negative input. the differential voltage across csip and csin is used to sense the ac adapter current, and is compared with the ac adapter current limit to regulate the ac adapter current. gnd gnd is an analog ground. dcin the dcin pin is the input of the internal 5v ldo. connect it to the ac adapter output. connect dcin to a 0.1 f ceramic capacitor. acset acset is an ac adapter detection input. connect to a resistor divider from the adapter input. acprn acprn is an ac adapter present open drain output. acprn is active low when acset is higher than typically 1.26v, and active high when acset is lower than typically 1.26v. en en is the charge enable input. connecting en to high enables the charge control fu nction, connecting en to low disables charging functions. us e with a thermistor to detect a hot battery and suspend charging. icm icm is the adapter current ou tput. the output of this pin produces a voltage proportion al to the adapter current. pgnd pgnd is the power ground. connect pgnd to the source of the low side mosfet for the low side mosfet gate driver. vdd vdd is an internal ldo output to supply ic analog circuit. connect a 1 f ceramic capacitor to ground. vddp vddp is the supply voltage for the low-side mosfet gate driver. connect a 4.7 ? resistor to vdd and a 1 f ceramic capacitor to power ground. icomp icomp is a current loop error amplifier output. vcomp vcomp is a voltage loop amplifier output. cells this pin is used to select the battery voltage. cells=vdd for a 4s battery pack, cells=gnd for a 3s battery pack, cells=float for a 2s battery pack. vadj vadj adjusts battery regulation voltage. vadj=vref for 4.2v+5%/cell; vadj=floating for 4.2v/cell; vadj=gnd for 4.2v-5%/cell. connect to a resistor divider to program the desired battery cell voltage between 4.2v-5% and 4.2v+5%. chlim chlim is the battery charge current limit set pin. chlim input voltage range is 0.1v to 3.6v. when chlim=3.3v, the set point for csop-cson is 165mv. the charger shuts down if chlim is forced below 88mv. aclim aclim is the adapter current limit set pin. aclim=vref for 100mv, aclim=floating for 75mv, and aclim=gnd for 50mv. connect a resistor divider to program the adapter current limit threshold between 50mv and 100mv. vref vref is a 2.39v reference output pin. it is internally compensated. do not connect a decoupling capacitor. isl6251, isl6251a
9 fn9202.1 june 17, 2005 figure 11. functional block diagram chlim cson csop + - boot acprn vddp cells vadj gnd vcomp acset + - aclim 1.27v 2.1v icomp csin csip + icm + - gm2 gm3 ca2 gm1 ca1 voltage selector ldo regulator phase vddp lgate adapter current limit set 0.25 v ca2 ugate pwm + - reference vref min voltage buffer vdd v ca2 + + - en 1.065v + - min current buffer + - + - acprn cells vadj gnd vcomp acset + aclim 1.26v chlim icomp csin csip icm + - gm2 gm3 voltage selector regulator ldo regulator lgate pgnd 0.25v ca2 pwm + - pwm + - reference vref min voltage buffer min voltage buffer vdd v ca2 vdd en 1.06v + - + - dcin ca1 19.9 ca2 + 20 adapter current limit set min current buffer gm1 2.1v - - - + - + chlim cson csop + - boot acprn vddp cells vadj gnd vcomp acset + - + - aclim 1.27v 2.1v icomp csin csip + icm + - gm2 gm3 ca2 gm1 ca1 voltage selector ldo regulator ldo regulator phase vddp lgate adapter current limit set 0.25 v ca2 ugate pwm + - pwm + - reference vref min voltage buffer min voltage buffer vdd v ca2 + + + - en 1.065v + - min current buffer min current buffer + - + - acprn cells vadj gnd vcomp acset + aclim 1.26v chlim icomp csin csip icm + - gm2 gm3 voltage selector regulator ldo regulator lgate pgnd 0.25v ca2 pwm + - pwm + - reference vref min voltage buffer min voltage buffer vdd v ca2 vdd en 1.06v + - + - dcin ca1 19.9 ca2 + 20 adapter current limit set min current buffer min current buffer gm1 2.1v - - - + - + isl6251, isl6251a
10 fn9202.1 june 17, 2005 figure 12. isl6251, isl6251a typical application circuit with fixed charging parameters csip csin boot ugate phase lgate pgnd csop cson cells icm gnd dcin acset vddp vdd acprn icomp vcomp vadj en chlim aclim vref q1 q2 l 10h c1 10f system load c10 10f r1 40m ? ac adapter r2 20m ? r3 18 ? r4 2.2 ? r6:10k r5 100k r8 130k 1% r9 10.2k 1% c2 0.1f c4 0.1f c3 1f c5:10nf c6:6.8nf c9 1f isl6251 isl6251a floating 4.2v/cell r10 4.7 ? c7 1f 3.3v battery pack bat+ bat- vdd 4 cells d1 optional d2 vddp vref r12 20k 1% r11 130k 1% r13 1.87k 1% 2.6a charge limit 253ma trickle charge c11 3300pf q3 trickle charge enable d4 to host controller charge enable csip csin boot ugate phase lgate pgnd csop cson cells icm gnd dcin acset vddp vdd acprn icomp vcomp vadj en chlim aclim vref q1 c8 0.1f isl6251 isl6251a floating 4.2v/cell c7 d3 r7: 100 ? charge enable isl6251, isl6251a
11 fn9202.1 june 17, 2005 dcin acset vddp vdd acprn chlim en icm aclim vref icomp vcomp vadj q1 q2 l 10h c1 10f c10 10f r1 40m ? ac adapter r2 20m ? r4 2.2 ? r5 100k r8 130k 1% r9 10.2k,1% c2 0.1f c4 0.1f c3 1f 6.8nf c9 1f c8 0.1f isl6251 isl6251a c5 10nf floating 4.2v/cell r6 10k c7 1f r10 4.7 ? battery pack bat+ scl sdl temp bat- scl sdl a/d input gnd 5.15a input current limit 3 cells host r11, r12, r13 10k d1 optional vddp d2 d3 r7: 100 ? csip csin boot ugate phase lgate pgnd csop cson cells gnd c11 3300pf d4 system load dcin acset vddp vdd acprn chlim en icm aclim vref icomp vcomp vadj r3: 18 ? c6 isl6251 isl6251a battery pack bat+ scl sdl temp bat- battery pack bat+ scl sdl temp bat- vcc output d/a output a/d input digital input avdd/vref csip csin boot ugate phase lgate pgnd csop cson cells gnd figure 13. isl6251, isl6251a typical application circuit with micro-controller isl6251, isl6251a
12 fn9202.1 june 17, 2005 theory of operation introduction the isl6251, isl6251a includes all of the functions necessary to charge 2 to 4 cell li-ion and li-polymer batteries. a high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10a. the isl6251, isl6251a has input current limiting and analog inputs for setting the charge current and charge voltage; chlim inputs are used to control charge current and vadj inputs are used to control charge voltage. the isl6251, isl6251a charges the battery with constant charge current, set by chlim input, until the battery voltage rises up to a programmed charge voltage set by vadj input; then the charger begins to operate at a constant voltage charge mode. the en input allows shutdown of the charger through a command from a micro-controller. it also uses en to safely shutdown the charger when the battery is in extremely hot conditions. the amount of adapt er current is reported on the icm output. figure 11 shows the ic functional block diagram. the synchronous buck converter uses external n-channel mosfets to convert the input voltage to the required charging current and charging voltage. figure 12 shows the isl6251, isl6251a typical application circuit with charging current and charging voltage fixed at specific values. the typical application circuit shown in figure 13 shows the isl6251, isl6251a typical application circuit which uses a micro-controller to adjust the charging current set by chlim input. the voltage at chlim and the value of r1 sets the charging current. the dc/dc converter generates the control signals to drive two external n-channel mosfets to regulate the voltage and current set by the aclim, chlim, vadj and cells inputs. the isl6251, isl6251a features a voltage regulation loop (vcomp) and two current regulation loops (icomp). the vcomp voltage regulation loop monitors cson to ensure that its voltage never exceeds the voltage and regulates the battery charge voltage set by vadj. the icomp current regulation loops regulate the battery charging current delivered to the battery to ensure that it never exceeds the charging current limit set by chlim; and the icomp current regulation loops also regulate the input current drawn from the ac adapter to ensure that it never exceeds the input current limit set by aclim, and to prevent a system crash and ac adapter overload. pwm c o ntrol the isl6251, isl6251a employs a fixed frequency pwm current mode control architecture with a feed forward function. the feed-forward function maintains a constant modulator gain of 11 to achieve fast line regulation as the buck input voltage changes. when the battery charge voltage approaches the input voltage, the dc/dc converter operates in dropout mode, where there is a timer to prevent the frequency from dropping into the audible frequency range. it can achieve duty cycle of up to 99.6%. to prevent boosting of the syst em bus voltage, the battery charger operates in standard-buck mode when csop- cson drops below 4.25mv. once in standard-buck mode, hysteresis does not allow synchronous operation of the dc/dc converter until csop-cson rises above 12.5mv. an adaptive gate drive scheme is used to control the dead time between two switches. the dead time control circuit monitors the lgate output an d prevents the upper side mosfet from turning on until lgate is fully off, preventing cross-conduction and shoot-through. in order for the dead time circuit to work properly, there must be a low resistance, low inductance path from the lgate driver to mosfet gate, and from the source of mosfet to pgnd. the external schottky diode is between the vddp pin and boot pin to keep the bootstrap capacitor charged. setting the battery regulation voltage the isl6251, isl6251a uses a high-accuracy trimmed band-gap voltage reference to regulate the battery charging voltage. the vadj input adjusts the charger output voltage, and the vadj control voltage can vary from 0 to vref, providing a 10% adjustment range (from 4.2v-5% to 4.2v+5%) on cson regulation voltage. an overall voltage accuracy of better than 0.5% is achieved. the per-cell battery termination voltage is a function of the battery chemistry. consult t he battery manufacturers to determine this voltage. ? float vadj to set the battery voltage v cson =4.2v number of the cells, ? connect vadj to vref to set 4.41v number of cells, ? connect vadj to ground to set 3.99v number of the cells. so, the maximum battery voltage of 17.6v can be achieved. note that other battery charge voltages can be set by connecting a resistor divider from vref to ground. the resistor divider should be sized to draw no more than 100a from vref; or connect a low impedance voltage source like the d/a converter in the micro-controller. the programmed battery voltage per cell can be determined by the following equation: connect cells as shown in table 1 to charge 2, 3 or 4 li+ cells. when charging other cell chemistries, use cells to select an output voltage range for the charger. the internal error amplifier gm1 maintains voltage regulation. the voltage error amplifier is compensated at vcomp. the component values shown in figure 12 provide suitable performance for most applications. individual compensation of the voltage v 3.99 v 175 . 0 v vadj cell + = isl6251, isl6251a
13 fn9202.1 june 17, 2005 regulation and current-regulation loops allows for optimal compensation. setting the battery charge current limit the chlim input sets the maximum charging current. the current set by the current sens e-resistor connects between csop and cson. the full-scale differential voltage between csop and cson is 165mv for chlim=3.3v, so the maximum charging current is 4.125a for a 40m ? sensing resistor. other battery char ge current-sense threshold values can be set by connecting a resistor divider from vref or 3.3v to ground, or by connecting a low impedance voltage source like a d/a conv erter in the micro-controller. the charge current limit threshold is given by: to set the trickle charge current for the dumb charger, a resistor in series with a switch q3 (figure 12) controlled by the micro-controller is connecte d from chlim pin to ground. the trickle charge current is determined by: when the chlim voltage is below 88mv (typical), it will disable the battery charger. when choosing the current sensing resistor, note that the voltage drop across the sensing resistor causes further power dissipation, reducing efficiency. however, adjusting chlim voltage to reduce the voltage across the current sense resistor r1 will degrade accuracy due to the smaller signal to the input of the current sense amplifier. there is a trade-off between accuracy and power dissipation. a low pass filter is recommended to eliminate switching noise. conne ct the resistor to the csop pin instead of the cson pin, as the csop pin has lower bias current and less influence on current-sense accuracy and voltage regulation accuracy. setting the input current limit the total input current from an ac adapter, or other dc source, is a function of the system supply current and the battery-charging current. the in put current regulator limits the input current by reducing the charging current, when the input current exceeds the input current limit set point. system current normally fluctuat es as portions of the system are powered up or down. without input current regulation, the source must be able to supply the maximum system current and the maximum charger input current simultaneously. by using the input current limiter, the current capability of the ac adapter can be lowered, reducing system cost. the isl6251, isl6251a limits t he battery charge current when the input current-limit threshold is exceeded, ensuring the battery charger does not load down the ac adapter voltage. this constant input current regulation allows the adapter to fully power the system and prevent the ac adapter from over loading and crashi ng the system bus. an internal amplifier gm3 compares the voltage between csip and csin to the input current limit threshold voltage set by aclim. connect aclim to ref, float and gnd for the full-scale input current limit threshold voltage of 100mv, 75mv and 50mv, respectively, or use a resistor divider from vref to ground to set the input current limit as the following equation: when choosing the current sens e resistor, note that the voltage drop across this resistor causes further power dissipation, reducing efficien cy. the ac adapter current sense accuracy is very important. use a 1% tolerance current-sense resistor. the highest accuracy of 3% is achieved with 100mv current-sense threshold voltage for aclim=vref, but it has the highest power dissipation. for example, it has 400mw power dissipation for rated 4a ac adapter and 1w sensing resistor may have to be used. 4% and 6% accuracy can be achieved with 75mv and 50mv current-sense threshold voltage for aclim=floating and aclim=gnd, respectively. a low pass filter is suggested to eliminate the switching noise. connect the resistor to csin pin instead of csip pin because csin pin has lower bias current and less influence on the current-sense accuracy. ac adapter detection connect the ac adapter voltage through a resistor divider to acset to detect when ac power is available, as shown in figure 12. acprn is an open-drain output and is high when acset is less than v th,rise , and active low when acset is above v th,fall . v th,rise and v th,fall are given by: where i hys is the acset input bias current hysteresis and v acset = 1.24v (min), 1.26v (typ.) and 1.28v (max.). the hysteresis is i hys r 8 , where i hys =2.2a (min.), 3.4a (typ.) and 4.4a (max.). table 1. cell number programming cells cell number vdd 4 gnd 3 float 2 i chg 165mv r 1 ------------------- v chlim 3.3v --------------------- - = i chg 165mv r 1 ------------------- v chlim trickle , 3.3v --------------------------------------- - = ? ? ? ? ? ? + = 050 . 0 v vref 05 . 0 r 1 i aclim 2 input acset 9 8 rise , th v 1 r r v ? ? ? ? ? ? ? ? ? + = 8 hys acset 9 8 fall , th r i v 1 r r v ? ? ? ? ? ? ? ? ? ? + = isl6251, isl6251a
14 fn9202.1 june 17, 2005 current measurement use icm to monitor the input current being sensed across csip and csin. the output vo ltage range is 0 to 2.5v. the voltage of icm is proportional to the voltage drop across csip and csin, and is given by the following equation: where i input is the dc current drawn from the ac adapter. icm has 3% accuracy. a low pass filter connected to ic m output is used to filter the switching noise. ldo regulator vdd provides a 5.075v supply voltage from the internal ldo regulator from dcin and can deliver up to 30ma of current. the mosfet drivers are powered by vddp, which must be connected to vddp as shown in figure 12. vddp connects to vdd through an external resistor. bypass vddp and vdd with a 1f capacitor. shutdown the isl6251, isl6251a features a low-power shutdown mode. driving en low shuts down the charger. in shutdown, the dc/dc converter is disabled, and vcomp and icomp are pulled to ground. the icm, acprn outputs continue to function. en can be driven by a thermistor to allow automatic shutdown when the battery pack is hot. often a ntc thermistor is included inside the battery pack to measure its temperature. when connected to the charger, the thermistor forms a voltage divider with a resistive pull-up to the vref. the threshold voltage of en is 1.06v with 60mv hysteresis. the thermistor can be selected to have a resistance vs temperature characteristic t hat abruptly decreases above a critical temperature. this arrangement automatically shuts down the charger when the battery pack is above a critical temperature. another method for inhibiting charging is to force chlim below 88mv (typ.). short circuit protection and 0v battery charging since the battery charger will regulate the charge current to the limit set by chlim, it aut omatically has short circuit protection and is able to provide the charge current to wake up an extremely discharged battery. over temperature protection if the die temp exceeds 150c, it stops charging. once the die temp drops below 125c, charging will start up again. application information the following battery charger design refers to the typical application circuit in figure 12, where typical battery configuration of 4s2p is used. this section describes how to select the external components including the inductor, input and output capacitors, switching mosfets, and current sensing resistors. inductor selection the inductor selection has trade-offs between cost, size and efficiency. for example, the lower the inductance, the smaller the size, but ripple current is higher. this also results in higher ac losses in the magnetic core and the windings, which decrease the system effi ciency. on the other hand, the higher inductance results in lower ripple current and smaller output filter capacito rs, but it has higher dcr (dc resistance of the inductor) loss, and has slower transient response. so, the practical inductor design is based on the inductor ripple current being (15-20)% of the maximum operating dc current at maximum input voltage. the required inductance can be calculated from: where v in,max , v bat , and f s are the maximum input voltage, battery voltage and switching frequency, respectively. the inductor ripple current ? i is found from: where the maximum peak-to-peak ripple current is 30% of the maximum charge current is used. for v in,max =19v, v bat =16.8v, i bat,max =2.6a, and f s =300khz, the calculated inductance is 8.3h. choosing the closest standard value gives l=10h. ferrite cores are often the best choice since they are optimized at 300khz to 600khz operation with low core loss. the core must be large enough not to saturate at the peak inductor current i peak : output capacitor selection the output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and smooth the output voltage. the rms value of the output ripple current i rms is given by: where the duty cycle d is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode which is typical operation for the battery charger. during the battery ch arge period, the output voltage varies from its initial battery voltage to the rated battery voltage. so, the duty cycle change can be in the range of icm 19.9 i input r 2 ? ? = s max , in bat l bat max , in f v v i v v l ? ? = max bat, l i 30% i ? = ? l max , bat peak i 2 1 i i ? + = () d 1 d f l 12 v i s max , in rms ? = isl6251, isl6251a
15 fn9202.1 june 17, 2005 between 0.53 and 0.88 for the minimum battery voltage of 10v (2.5v/cell) and the maximu m battery voltage of 16.8v. for v in,max =19v, vbat=16.8v, l=10h, and f s =300khz, the maximum rms current is 0. 19a. a typical 10f ceramic capacitor is a good choice to absorb this current and also has very small size. the tantalum capacitor has a known failure mechanism when subjected to high surge current. emi considerations usually make it desirable to minimize ripple current in the battery leads. beads may be added in series with the battery pack to increase the battery impedance at 300khz switching frequency. switching ripple current splits between the battery and the output capacitor depending on the esr of the ou tput capacitor and battery impedance. if the esr of the output capacitor is 10m ? and battery impedance is raised to 2 ? with a bead, then only 0.5% of the ripple current will flow in the battery. mosfet selection the notebook battery charger synchronous buck converter has the input voltage from the ac adapter output. the maximum ac adapter output voltage does not exceed 25v. therefore, 30v logic mosfet should be used. the high side mosfet must be able to dissipate the conduction losses plus the switching losses. for the battery charger application, the input voltage of the synchronous buck converter is equal to the ac adapter output voltage, which is relatively constant. the maximum efficiency is achieved by selecting a high side mosfet that has the conduction losses equal to the s witching losses. ensure that isl6251 lgate gate driver can supply sufficient gate current to prevent it from conduction, which is due to the injected current into the drai n-to-source parasitic capacitor (miller capacitor c gd ), and caused by the voltage rising rate at phase node at the time inst ant of the high-side mosfet turning on; otherwise, cross-conduction problems may occur. reasonably slowing turn-on speed of the high-side mosfet by connecting a resistor between the boot pin and gate drive supply source, and the high sink current capability of the low-side mosf et gate driver help reduce the possibility of cross-conduction. for the high-side mosfet, the worst-case conduction losses occur at the minimum input voltage: the optimum efficiency occurs when the switching losses equal the conduction losses. however, it is difficult to calculate the switching losses in the high-side mosfet since it must allow for diff icult-to-quantify factors that influence the turn-on and turn-off times. these factors include the mosfet internal gate resistance, gate charge, threshold voltage, stray inductance, pull-up and pull-down resistance of the gate driver. the following switching loss calculation provides a rough estimate. where q gd : drain-to-gate charge, q rr : total reverse recovery charge of the body-diode in low side mosfet, i lv : inductor valley current, i lp: inductor peak current, i g,sink and i g , source are the peak gate-drive source/sink current of q1, respectively. to achieve low switching losses, it requires low drain-to-gate charge q gd . generally, the lower the drain-to-gate charge, the higher the on-resistance. th erefore, there is a trade-off between the on-resistance and drain-to-gate charge. good mosfet selection is based on the figure of merit (fom), which is a product of the total gate charge and on- resistance. usually, the smaller the value of fom, the higher the efficiency for the same application. for the low-side mosfet, the worst-case power dissipation occurs at minimum battery voltage and maximum input voltage: choose a low-side mosfet th at has the lowest possible on-resistance with a moderate-sized package like the so-8 and is reasonably priced. the switching losses are not an issue for the low side mosfet because it operates at zero- voltage-switching. choose a schottky diode in parallel with low-side mosfet q2 with a forward voltage drop low enough to prevent the low-side mosfet q2 body-diode from turning on during the dead time. this also reduces the power loss in the high-side mosfet associated with the reverse recovery of the low- side mosfet q2 body diode. as a general rule, select a diode with dc current rating equal to one-third of the load current. one option is to choose a combined mosfet with the schottky diode in a single package. the integrated packages may work better in practice because there is less stray inductance due to a short connection. this schottky diode is optional and may be removed if efficien cy loss can be tolera ted. in addition, ensure that the required total gate drive current for the selected mosfets should be less than 24ma. so, the total gate charge for the high-side and low-side mosfets is limited by the following equation: where i gate is the total gate drive current and should be less than 24ma. substituting i gate =24ma and f s =300khz into the above equation yields that the total gate charge dson 2 bat in out conduction , 1 q r i v v p = s in rr k sin , g gd s lp in source , g gd s lv in switching , 1 q f v q i q f i v 2 1 i q f i v 2 1 p + + = dson 2 bat in out 2 q r i v v 1 p ? ? ? ? ? ? ? ? ? = s gate gate f i q isl6251, isl6251a
16 fn9202.1 june 17, 2005 should be less than 80nc. therefore, the isl6251 easily drives the battery charge current up to 10a. input capacitor selection the input capacitor absorbs the ripple current from the synchronous buck converter, which is given by: this rms ripple current must be smaller than the rated rms current in the capacitor datas heet. non-tantalum chemistries (ceramic, aluminum, or oscon) are preferred due to their resistance to power-up surge currents when the ac adapter is plugged into the battery charger. for notebook battery charger applications, it is recommend that ceramic capacitors or polymer capacitors from sanyo be used due to their small size and reasonable cost. table 2 shows the component lists for the typical application circuit in figure 12. loop compensation design isl6251 uses constant frequ ency current mode control architecture to achieve fast loop transient response. accurate current sensing resistors in series with the output inductor is used to regulate the charge current, and the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design. the inductor is not considered as a state variable for current mode control and the system becomes single order system. it is much easier to design a compensator to stabilize the voltage loop than voltage mode control. figure 14 shows the small signal model of the synchronous buck regulator. pwm comparator gain f m : the pwm comparator gain fm for peak current mode control is given by: where v pwm is the peak-peak voltage of the pwm ramp signal. current sampling transfer function h e (s): in current loop, the current sig nal is sampled every switching cycle. it has the followi ng transfer function: where q n and n are given by n = f s , respectively. power stage transfer functions transfer function f 1 (s) from control to output voltage is: where , transfer function f 2 (s) from control to inductor current is: , where . current loop gain t i (s) is expressed as the following equation: where r t is the trans-resistance in current loop. r t is usually equal to the product of the current sensing resistance of the current amplifier. for isl6251, r t =20r 1 . table 2. compon e nt list parts part numbers and manufacturer c1, c10 10 f/25v ceramic capacitor, taiyo yuden tmk325 mj106my x5r (3.2x2.5x1.9mm) c2, c4, c8 0.1 f/50v ceramic capacitor c3, c7, c9 1 f/10v ceramic capacitor, taiyo yuden lmk212bj105mg c5 10nf ceramic capacitor c6 6.8nf ceramic capacitor c11 3300pf ceramic capacitor d1 30v/3a schottky diode, ec31qs03l (optional) d2, d3 100ma/30v schottky diode, central semiconductor d4 8a/30v schottky rectifier, stps8l30b (optional) l10 h/3.8a/26m ? , sumida, cdrh104r-100 q1, q2 30v/35m ? , fds6912a, fairchild. q3 signal n-channel mosfet, 2n7002 r1 40m ? , 1%, lrc-lr2512-01-r040-f, irc r2 20m ? , 1%, lrc-lr2010-01-r020-f, irc r3 18 ? , 5%, (0805) r4 2.2 ? , 5%, (0805) r5 100k ? , 5%, (0805) r6 10k, 5%, (0805) r7 100 ? , 5%, (0805) r8, r11 130k, 1%, (0805) r9 10.2k ? , 1%, (0805) r10 4.7 ? , 5%, (0805) r12 20k ? , 1%, (0805) r13 1.87k ? , 1%, (0805) () in out in out bat rms v v v v i i ? = pwm comp m v 1 v ? d ? f = = () 1 q s s s h n n 2 n 2 e + + = , 2 q n ? = () 1 q s s s 1 v d ? v ? s f p o 2 o 2 esr in o 1 + + + = = , c r 1 o c esr = l c r q o o p o o lc 1 = () 1 q s s s 1 r r v d ? i ? s f p o 2 o 2 z l o in l 2 + + + + = = o o z c r 1 () () s h s f f r ) s ( t e 2 m t i = isl6251, isl6251a
17 fn9202.1 june 17, 2005 the voltage gain with open current loop is: where , v fb is the feedback voltage of the voltage error amplifier. the voltage loop gain with current loop closed is given by: if t i (s)>>1, then it can be simplified as follows: , from the above equation, it is shown that the system is a single order system, which has a single pole located at before the half sw itching frequency. therefore, simple type ii compensator can be easily used to stabilize the system. figure 15 shows the voltage loop compensator, and its transfer function is expressed as follows: figure 14. small signal model of synchronous buck regulator figure 15. voltage loop compensator where compensator design goal: ? high dc gain ? loop bandwidth f c : ? gain margin: >10db ? phase margin: 40 the compensator design procedure is as follows: 1. put compensator zero at: 2. put one compensator pole at zero frequency to achieve high dc gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower. the loop gain t v (s) at cross over frequency of f c has unity gain. therefore, the compensator resistance r 1 is determined by: where g m is the trans-conductance of the voltage loop error amplifier. compensator capacitor c1 is then given by: example: v in =19v, v o =16.8v, i o =2.6a, f s =300khz, c o =10 f/10m ? , l=10 h, g m =250 s, r t =0.2 ? , v fb =2.1v, v pwm =v in /11, f c =20khz, then compensator resistance r 1 =8.0k ? . choose r 1 =10k ? . put the compensator zero at 1.5khz. the compensa tor capacitor is c 1 =10nf. therefore, choose voltage loop compensator: r 1 =10k, c 1 =10nf. pcb layout considerations power and signal layers placement on the pcb as a general rule, power layers should be close together, either on the top or bottom of th e board, with signal layers on the opposite side of the board. as an example, layer arrangement on a 4-layer board is shown below: 1. top layer: signal lines, or half board for signal lines and the other half board for power lines 2. signal ground 3. power layers: power ground 4. bottom layer: power mosfet, inductors and other power traces separate the power voltage and current flowing path from the control and logic level signal path. the controller ic will () () s a s f kf ) s ( t v 1 m v = o fb v v k = () () s t 1 s t ) s ( l i v v + = () () s h s a s 1 s 1 r r r v v ) s ( l e v p esr t l o o fb v + + + = o o p c r 1 p d ? v in d ? i l in v ? in i ? l + 1:d + l i ? co rc ro -av(s) d ? comp v ? r t fm he(s) + t i (s) k o v ? t v (s) d ? v in d ? i l in v ? in i ? l + 1:d + l i ? co rc ro -av(s) d ? comp v ? r t fm he(s) + t i (s) k o v ? t v (s) - + r1 c1 v ref v fb vo g m v comp - + vo - + r1 c1 v ref v fb vo g m v comp - + vo () sc s 1 g v ? v ? s a 1 cz m fb comp v + = = , c r 1 1 1 cz = s f 20 1 5 1 ? ? ? ? ? ? ? () o o cz c r 1 3 1 ? = fb m t o o c 1 v g r c v f 2 r = cz 1 1 r 1 c = isl6251, isl6251a
18 fn9202.1 june 17, 2005 stay on the signal layer, which is isolated by the signal ground to the power signal traces. component placement the power mosfet should be close to the ic so that the gate drive signal, the lgate, ugate, phase, and boot, traces can be short. place the components in such a way that the area under the ic has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. signal ground and power ground connection. at minimum, a reasonably large area of copper, which will shield other noise couplings through the ic, should be used as signal ground beneath the ic. the best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the ic is not recommended. gnd and vdd pin at least one high quality ceramic decoupling cap should be used to cross these two pins. the decoupling cap can be put close to the ic. lgate pin this is the gate drive signal for the bottom mosfet of the buck converter. the signal going through this trace has both high dv/dt and high di/dt, and the peak charging and discharging current is very high. these two traces should be short, wide, and away from other traces. there should be no other traces in parallel with these traces on any layer. pgnd pin pgnd pin should be laid out to the negative side of the relevant output cap with separate traces. the negative side of the output capacitor must be close to the source node of the bottom mosfet. this trace is the return path of lgate. phase pin this trace should be short, a nd positioned away from other weak signal traces. this node has a very high dv/dt with a voltage swing from the input voltage to ground. no trace should be in parallel with it. this trace is also the return path for ugate. connect this pin to the high-side mosfet source. ugate pin this pin has a square shape waveform with high dv/dt. it provides the gate drive current to charge and discharge the top mosfet with high di/dt. this trace should be wide, short, and away from other traces similar to the lgate. boot pin this pin?s di/dt is as high as the ugate; therefore, this trace should be as short as possible. csop, cson pins the current sense resistor co nnects to the cson and the csop pins through a low pass filter. the cson pin is also used as the battery voltage f eedback. the traces should be away from the high dv/dt and di/di pins like phase, boot pins. in general, the current sense resistor should be close to the ic. other layout arrangements should be adjusted accordingly. en pin this pin stays high at enable mode and low at idle mode and is relatively robust. enable signals should refer to the signal ground. dcin pin this pin connects to ac adapter output voltage, and should be less noise sensitive. copper size for the phase node the capacitance of phase shoul d be kept very low to minimize ringing. it would be be st to limit the size of the phase node copper in strict accordance with the current and thermal management of the application. identify the power and signal ground the input and output capacitors of the converters, the source terminal of the bottom switch ing mosfet pgnd should connect to the power ground. the other components should connect to signal ground. signal and power ground are tied together at one point. clamping capacitor for switching mosfet it is recommended that ceramic caps be used closely connected to the drain of th e high-side mosfet, and the source of the low-side mosfet . this capacitor reduces the noise and the power loss of the mosfet. isl6251, isl6251a
19 fn9202.1 june 17, 2005 isl6251, isl6251a quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l28.5x5 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-1 issue i) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - 0.02 0.05 - a2 - 0.65 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.20 - - - l 0.50 0.60 0.75 8 n282 nd 7 3 ne 7 3 p- -0.609 --129 rev. 1 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation.
20 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9202.1 june 17, 2005 isl6251, isl6251a shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual in- dex feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dam- bar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. c onverted millimeter dimensions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m24.15 24 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - a2 - 0.061 - 1.54 - b 0.008 0.012 0.20 0.30 9 c 0.007 0.010 0.18 0.25 - d 0.337 0.344 8.55 8.74 3 e 0.150 0.157 3.81 3.98 4 e 0.025 bsc 0.635 bsc - h 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 l 0.016 0.050 0.41 1.27 6 n24 247 0 8 0 8 - rev. 2 6/04

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